FIG. 1 depicts in block diagram form a prior art clock signal generator 10 for providing an adjustable frequency clock signal CLOCK synchronized to a reference clock signal ROSC provided by a stable oscillator 12. Clock signal generator 10 includes a set of N logic gates 14 connected in series to form a delay line 16 providing a set of N tap signals T0-TN-1 at the outputs of gates 14. Each gate 14 has a signal delay of TP/N so that each tap signal Tk is delayed with respect to the ROSC signal by an interval of PD=(k/N)*TP, where Tp is the period of the ROSC signal.
The ROSC signal and tap signal TN serve as inputs to a conventional phase lock (PL) controller 18 supplying a control signal (CONTROL) to all gates 14. The magnitude of the CONTROL signal controls the switching speed of the gates 14. When tap signal TN lags the ROSC signal, controller 18 sets the CONTROL signal voltage to increase the switching speed of gates 14, and when tap signal TN leads the ROSC signal, controller 18 adjusts the CONTROL signal voltage to decrease the switching speed of gates 14. Thus controller 18 compares signal ROSC to signal TN and adjusts the switching speed of all gates 14 to phase lock the TN signal to the ROSC signal, thereby making each gate 14 have the desired signal delay of TP/N.
A multiplexer 20 having N+1 inputs 0-N produces the output signal CLOCK. Tap signals T0-TN-1 drive inputs 0-(N−1) of multiplexer 20 and input N of multiplexer 20 is grounded. Multiplexer 20 controls the timing of each pulse edge of the CLOCK signal by selecting one of its input signals. A sequencer 22 responds to each ROSC signal pulse by providing control data SW telling multiplexer 20 which input signal T0-TN-1 (or ground) to select. Delay line 16, PL controller 18 and multiplexer 20 form a programmable delay circuit 24 for delaying any ROSC signal pulse with a delay determined by the input SW data to produce a CLOCK signal pulse. The sequence of SW data values therefore controls the timing of each pulse of the CLOCK signal, and thereby controls the phase and frequency of the CLOCK signal.
FIG. 2 is a timing diagram illustrating various signals associated with clock signal generator 10 of FIG. 1 in which N=5 and thus five gates 14 form delay line 16. In this example the five gates provide five tap signals T0-T4 as input signals to multiplexer 20 inputs 0-4. Multiplexer input T5 is grounded. The ROSC signal and input signals T0-T4 all have the same frequency. Input signal T1 is delayed with respect to the ROSC signal by PD=TP/5, the switching delay of one gate 14. Each successive signal of the remaining input signals Tk is delayed with respect to the ROSC signal by k*PD. Thus, for example, T4 is delayed with respect to the ROSC signal by 4PD.
FIG. 2 also illustrates examples CLOCK(a)-CLOCK(d) of output signal CLOCK provided in response to four different SW signal patterns produced by sequencer 22 of FIG. 1. Suppose we want an output signal CLOCK(a) having the same frequency as ROSC but being shifted in phase by 2PD. To do this we program sequencer 22 to set signal SW so that multiplexer 20 selects input signal T2 on each cycle of the ROSC signal. Thus, signal SW supplies a sequence of data values to multiplexer 20 of the form SW={2, 2, 2, . . . }. As shown in FIG. 2 the resultant signal CLOCK(a) is shifted in phase by 2P with respect to the ROSC signal.
Alternatively, when we want clock signal generator 10 to produce an output signal CLOCK(b) having a period equal to 1.2 TP, we program sequencer 22 to set signal SW to value SW=0 for the first ROSC period and then switch signal SW to value SW=1 at the start of the second ROSC period and so on. Since CLOCK(b) is of lower frequency than ROSC, sequencer 22 must occasionally instruct multiplexer 20 to select its grounded input 5. In this example this occurs during every sixth ROSC cycle. Thus, to produce CLOCK(b) signal SW is a repetitive sequence of the form SW={0, 1, 2, 3, 4, 5 . . . }.
When we want clock signal generator 10 to produce an output signal CLOCK(c) with a period equal to 1.4 TP, we program sequencer 22 to generate a repeating SW signal sequence of the form SW={0, 2, 4, 5, 1, 3, 5 . . . ). A repetitive SW sequence of the form SW={0, 5, 0, 5 . . . } produces an output signal CLOCK(d) with a period twice that of the ROSC signal, or 2 TP.
Thus, clock signal generator 10 can produce a variety of output clock signals CLOCK whose frequencies depend on the programming of sequencer 22. However, the resolution with which the clock signal generator 10 can adjust the period of the CLOCK output signal is limited to PD=TP/N, the delay of one gate 14.
By increasing the number N of gates 14 in delay line 16 we can improve the period resolution PD of clock signal generator 10. However, since all gates 14 must switch in succession during a single ROSC clock period, there is a limit to the number of gates that can be included in delay line 16. Thus, the resolution PD=TP/N of clock signal generator 10 can be no smaller than the minimum switching speed of gates 14.
FIG. 3 depicts in block diagram form a prior art clock signal generator 30 for generating clock signals with a higher period resolution than possible with clock signal generator 10 of FIG. 1. In FIG. 3 a stable oscillator 32 provides a ROSC pulse with period TP to a “coarse” delay circuit 34 similar to the programmable delay circuit 24 of FIG. 1 which can delay a pulse of the ROSC cycle to produce a CLOCK signal pulse with a delay of up to TP adjustable with a “coarse” resolution of TP/N. A “fine” delay circuit 38 further delays each CLOCK signal pulse with an adjustable delay over a narrow range of up to TP/N with a “fine” resolution of TP/(M*N). In response to each ROSC signal pulse, a programmable sequencer 36 provides SW(A) data to coarse delay circuit 34 telling it how much to delay the ROSC pulse to produce a CLOCK signal pulse and provides SW(B) data to fine delay circuit 38 telling it how much to delay the CLOCK pulse to produce a CLOCK′ signal pulse. Thus the total delay between a ROSC signal pulse and a corresponding CLOCK′ signal pulse is DT=j*TP/N+k*TP/(M*N), where 0≦j≦N and 0≦k≦M. Thus the period resolution of clock signal generator 30 is PD=TP/(M*N) over the range spanning TP.
FIG. 4 depicts prior art fine delay circuit 38 in more detailed block diagram form in an example where M=32. A set of five delay modules 40(1)-40(5) connect to the output of delay circuit 34 of FIG. 3. Each module 40(1)-40(5) has a pass gate 42 and a capacitor 44 connected in series between the CLOCK signal line and ground. Each bit SEL1-SEL5 of the input 5-bit control data SW(B) controls whether the pass gate 42 of a corresponding module 40(1)-40(5) is open or closed. When a gate 42 is open its respective capacitor 44 has no effect on a CLOCK signal pulse. When a gate 42 is closed its respective capacitor 44 increases the delay between the CLOCK and CLOCK′ signals.
In the example of FIG. 4 the capacitors 44 range in value from C to 16C where the value of C is chosen so that a total capacitance of kC is connected to the CLOCK signal line adding a delay of kTP/(M*N) to a CLOCK signal pulse. Thus a pulse of the CLOCK signal can be delayed over a range spanning up to TP/N with a delay resolution of TP/(M*N)=TP/(N*(25))=TP/32N to provide a CLOCK′ signal pulse, depending on the amount of capacitance gates 42 link to the CLOCK signal line.
In contrast to coarse delay circuit 34, where a delay line 16 (FIG. 1) is phase-locked to a stable reference signal ROSC and thus provides a highly accurate and “self-calibrating” delay resolution, delay modules 40(1)-40(5) of fine delay Circuit 38 must be calibrated to establish an accurate delay resolution for this circuit. The calibration process is difficult and time-consuming.
Thus we cannot increase the period resolution of the clock signal generator 10 of FIG. 1 by increasing the number N of gates 14 beyond that point at which the resolution becomes smaller than the minimum possible gate switching time. And, although we can enhance, the period resolution of clock signal generator 10 through the use of fine delay circuit 38 (FIG. 4), calibration of fine delay circuit 38 is problematic. Since many potentially useful applications for clock signal generators require higher clock period resolutions than are attainable with clock signal generator 10, what is needed is a self-calibrating clock signal generator with a high period resolution.